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Post  mario_marin on Mon Oct 31, 2011 10:52 am

1. In Interconnect-centric Design for Advanced SoC and NoC, we have tried to create a comprehensive understanding about on-chip interconnect characteristics, design methodologies, layered views on different abstraction levels and finally about applying the interconnect-centric design in system-on-chip design.

Taken from Tapani Ahonen et al. A brunch from the coffee table – case study in NoC platform design. In J. Nurmi, H. Tenhunen, J. Isoaho, and A. Jantsch, editors, Interconnect-Centric Design for Advanced SoC and NoC, pages 425–453. Kluwer Academic Publishers, 2004.

2. IEE Proceedings Computers & Digital Techniques publishes
technical papers describing recent research and development work in all
aspects of digital system-on-chip design and test of electronic and
embedded systems, including the development of design automation tools
(methodologies, algorithms and architectures). It is aimed at
researchers, engineers and educators in the fields of computer and
digital systems design and test.

Taken from M. Amde,
T. Felicijan, A. Efthymiou, D. Edwards, and L. Lavagno.
Asynchronous On-Chip Networks.
IEE Proceedings Computers and Digital Techniques, 152(02),

3. Thomas Ainsworth and Timothy Pinkston. On characterizing performance of the Cell broadband engine element interconnect bus. In Proc. of the ACM/IEEE Int. Symp. on Networks-on-Chip (NOCS), May 2007.

4. Daniel Åkerlund. Implementation of a 2x2 NoC with wishbone interface. Master's thesis, School for Information and Communication Technology, Royal Institute of Technology, Stockholm, Sweden, November 2005.


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