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Post  cesar_Arroyo on Mon Oct 31, 2011 10:51 am

1- taken from http://deya.forosactivos.net/post?f=49&mode=newtopic

2- taken from http://www.vlsichipdesign.com/index.php/Chip-Design-Articles/vlsidesignflow.html

3- taken from http://www.vlsichipdesign.com/index.php/Chip-Design-Articles/statictiminganalysis.html

"How many minimum modes i should qualify STA for a chip

- Scan Shift mode
- Scan Capture mode
- MBIST mode
- Functional modes for Each Interface
- Boundary scan mode
- scan-compression mode

How many minimum process lots , should STA be qualified.

- Fast corner
- Slow corner
- Typical corner

How many minimum Timing , Should STA be qualified.

- normal delay mode(with out applying deration)
- On-chip variation mode (deration applied)
- SI mode (Signal integrity cross talk impact on STA)"

this part of the article is about some diagrams of the yiming analysis in th e chip designing.

4- taken from http://www.vlsichipdesign.com/index.php/Chip-Design-Articles/asic-definition.html

"ASIC stands for the abbreviation of Application Specific Integrated Circuits. It means an integrated circuit designed for a specific application. An application could be a microprocessor, cell phone, modem, router, etc., The respective ASIC will have its own architecture, need to support its own protocol requirements . In todays ASIC has a complete system in a single often called as System on a Chip(SOC)."

The article is about the definition and some important concepts of chip designing

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